1. Field of the Invention
The invention relates to a shallow trench isolation (STI) of a semiconductor device and fabrication method thereof, and more particularly, to an STI of a semiconductor material fabricated by a multi-step deposition method with non-TEOS ramp up process.
2. Description of the Prior Art
In semiconductor products, silicon oxide materials and silicon nitride materials are generally used to form isolation structures for isolating electric elements or devices. Conventional oxide dielectric layers or isolation structures are fabricated by localized oxidation isolation (LOCOS) methods or thin film deposition processes. For example, some gases such as silane (SiH4), tetra-ethyl-ortho-silicate (TEOS) and oxygen are used in a thin film deposition process to form a dielectric layer. The chemical reaction between the gases forms a thin film on the semiconductor wafer to provide electrical insulation between devices.
In the fabrication process of semiconductor devices with line width less than 0.18 μm, shallow trench isolations are mainly utilized for being the isolation structures of active areas. The formation of an STI is to form a shallow trench near the surface of a semiconductor substrate and to fill a silicon oxide layer into the shallow trench for electrically isolating adjacent active areas. However, as the critical dimension of the integrated circuit devices shrinks to very deep sub-micron scale or beyond, it becomes more and more critical to completely fill silicon oxide layer into the shallow trenches for forming reliable and effective isolation structure in the art.
Conventional fabrication method of shallow trench isolations includes high density plasma chemical vapor deposition (HDCVD) method, which is utilized to form dielectric materials filling shallow trenches. After the formation of the dielectric materials, a chemical mechanical polishing (CMP) process is performed to remove the dielectric materials above the shallow trenches to leave a plan top surface of the shallow trench. However, conventional CVD methods have no longer provided satisfactory step coverage when dealing with high aspect ratio trenches, such as the trenches with aspect ratios more than 6, which are typically encountered in the fabrication of advanced integrated circuits under 65 nm scale semiconductor fabrication process.
To overcome this, ozone-assisted sub-atmospheric pressure chemical vapor deposition (SACVD) techniques have been developed. The ozone-assisted SACVD utilizes ozone and TEOS as the reactant gas to form conformal silicon oxide layer under a pressure of about 60 torrs. After the SACVD film deposition, a high-temperature nitrogen anneal is performed to densify the deposited SACVD film.
However, the prior art ozone-assisted SACVD techniques have several drawbacks when they are employed in the device isolation field. First, after the high-temperature anneal treatment, the deposited SACVD film is apt to shrink. For example, a shrinkage of about 7% has been observed after annealed at 1050° C. for 30 minutes. Besides, the film quality of the SACVD silicon oxide and its resistance to wet etchant are not high enough. Furthermore, the deposition sensitivity of the SACVD silicon oxide is not low enough.
Another problem encountered when employing SACVD to form trench isolation regions includes seams and voids occurring in the dielectric films in the trenches. Please refer to FIG. 1, which is a sectional schematic diagram of an STI formed by a conventional SACVD process. Since the silicon oxide layer film 12 formed by the SACVD film deposition is conformal and uniform along the sidewalls 16 of the trench 14, a seam defect 18 or a void defect 20 are left near the central line of the trench 14 when the trench 14 is filled up. The seam defect 18 and void defect 20 are concerned because they cannot be removed by mere high-temperature nitrogen anneal as mentioned supra, and because they are subject to corrosion or attacks by the wet etchant used in the subsequent wet cleaning procedures, which affects the performance of the semiconductor elements and causes polysilicon circuit shorts.
Recently, TEOS ramp-up SACVD method is brought up to fabricate a shallow trench isolation for improving the quality of silicon oxide layers formed by the conventional SACVD processes. The TEOS ramp-up SACVD method includes providing a continuous flow of a silicon-containing gas and a flow of an oxidizing processing gas to the reaction chamber to perform a SACVD process, wherein the silicon-containing gas flow rate continuously ramps up when depositing the silicon oxide layer into the trench. The TEOS ramp-up SACVD method may improve the deposition sensitivity of the silicon oxide layer. However, when the width of a trench is less than 65 nanometers or even less than 45 nanometers, the above-mentioned seam defect and void defect problems still occur in the silicon oxide layer formed by the TEOS ramp-up SACVD method.
Therefore, it is desirable to be able to fill narrow gaps with dielectric material in a void-free or a seam-free manner.